VMusic2 Vinculum VNC1L Module

Datasheet Version 0.98

© Future Technology Devices International Ltd. 2007

Page 

2.3 SPI Interface Signal Descriptions and Timing Diagrams

Ta�le �� � Data and Control ��us �ignal Mode �ptions � ��I Inter�ace

Pin No.

Name

Type

Description

�

�CLK

Input

��I Clock input�� 12MHz ma�imum.

4

�DI

Input

��I �erial Data Input

2

�D�

�utput

��I �erial Data �utput

6

C�

Input

��I Chip �elect Input

Figure 2 � ��I �lave Data �ead Cycle

SPICLK

SPI Data In

SPI Data Out

SPI CS

R/W ADD

D0

D1

D2

D3

D4

D5

D6

D7

1

1

0

From �tart � ��I C� must �e held high �or the entire read cycle�� and must �e taken low �or at least one clock period

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the chip. The ne�t �it is the address �it�� ��DD�� which is used to indicate whether the data register (�0�) or the status

register (�1�) is read �rom. During the ��I read cycle a �yte o� data will start �eing output on ��I Data �ut on the ne�t

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�ut should �e checked to see i� the data read is new data. �� �0� level here on ��I Data �ut means that the data read

is new data. �� �1� indicates that the data read is old data�� and the read cycle should �e repeated to get new data.

�emem�er that C� must �e held low �or at least one clock period �e�ore �eing taken high again to continue with the

ne�t read or write cycle.

Figure �� � ��I �lave Data Write Cycle

SPICLK

SPI Data In

SPI Data Out

SPI CS

R/W ADD

D0

D1

D2

D3

D4

D5

D6

D7

1

0

0

From �tart � ��I C� must �e held high �or the entire write cycle�� and must �e taken low �or at least one clock period

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to the chip. The ne�t �it is the address �it�� ��DD�� which is used to indicate whether the data register (�0�) or the status

register (�1�) is written to. During the ��I write cycle a �yte o� data can �e input to ��I Data In on the ne�t clock cycle

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