Operation descriptions

VIPER28

22/32

Doc ID 15028 Rev 5

Equation 7

Equation 8

The

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 24.

FB pin configuration (option 1)

Figure 25.

FB pin configuration (option 2)

f

PF B

R

FB DYN

()

R

FB1

+

2

π C

FB

R

FB DYN

()

R

FB1

⋅

()

⋅⋅

⋅

------------------------------------------------------------------------------------------

=

f

PFB

1

2

π C

FB1

R

FB1

R

FB DYN

()

⋅

()

⋅⋅

⋅

---------------------------------------------------------------------------------------------

=

From sense FET

4.8V

BURST

PWM

CONTROL

Cfb

To PWM Logic

BURST-MODE

REFERENCES

BURST-MODE

LOGIC

+

-

PWM

+

-

OLP comparator

To disable logic

4.8V

From sense FET

PWM

CONTROL

+

-

PWM

BURST

To disable logic

+

-

OLP comparator

To PWM Logic

BURST-MODE

LOGIC

Cfb1

Rfb1

Cfb

BURST-MODE

REFERENCES