STM32F415OG datasheet(131/186 Pages) STMICROELECTRONICS

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DocID022063 Rev 4

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STM32F415xx, STM32F417xx

Electrical characteristics

Equation 1: RAIN max formula

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of

sampling periods defined in the ADC_SMPR1 register.

tCONV(4)

Total conversion time (including

sampling time)

fADC = 30 MHz

12-bit resolution

0.50

16.40

µs

fADC = 30 MHz

10-bit resolution

0.43

16.34

µs

fADC = 30 MHz

8-bit resolution

0.37

16.27

µs

fADC = 30 MHz

6-bit resolution

0.30

16.20

µs

9 to 492 (tS for sampling +n-bit resolution for successive

approximation)

1/fADC

fS(4)

Sampling rate

(fADC = 30 MHz, and

tS = 3 ADC cycles)

12-bit resolution

Single ADC

Msps

12-bit resolution

Interleave Dual ADC

mode

3.75

Msps

12-bit resolution

Interleave Triple ADC

mode

Msps

IVREF+(4)

ADC VREF DC current

consumption in conversion

mode

-300

500

µA

IVDDA(4)

ADC VDDA DC current

consumption in conversion

mode

-1.6

1.8

1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of

an external power supply supervisor (refer to Section : Internal reset OFF).

2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.

3. VDDA -VREF+ < 1.2 V.

4. Based on characterization, not tested in production.

5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.

7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.

Table 67. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RAIN

k0.5

–

()

fADC CADC

()

--------------------------------------------------------------

RADC

–

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