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STM32F415OG 数据表(PDF) 133 Page - STMicroelectronics |
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STM32F415OG 数据表(HTML) 133 Page - STMicroelectronics |
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133 / 186 page  DocID022063 Rev 4 133/186 STM32F415xx, STM32F417xx Electrical characteristics EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. ai17534 STM32F VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) CADC(1) 12-bit converter Sample and hold ADC converter |
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