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LATA1 数据表(PDF) 42 Page - Microchip Technology |
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LATA1 数据表(HTML) 42 Page - Microchip Technology |
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42 / 478 page  PIC16(L)F1946/1947 DS41414D-page 42 2010-2012 Microchip Technology Inc. Bank 9 480h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 481h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 482h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 483h(2) STATUS — — —TO PD ZDC C ---1 1000 ---q quuu 404h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 485h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 486h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 487h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 488h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 489h(2) WREG Working Register 0000 0000 uuuu uuuu 48Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 48Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 48Ch — Unimplemented — — 48Dh WPUG — —WPUG5 — — — — — --1- ---- --1- ---- 48Eh — Unimplemented — — 48Fh — Unimplemented — — 490h — Unimplemented — — 491h RC2REG USART Receive Data Register 0000 0000 0000 0000 492h TX2REG USART Transmit Data Register 0000 0000 0000 0000 493h SP2BRGL EUSART2 Baud Rate Generator, Low Byte 0000 0000 0000 0000 494h SP2BRGH EUSART2 Baud Rate Generator, High Byte 0000 0000 0000 0000 495h RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 496h TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 497h BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 498h — Unimplemented — — 499h — Unimplemented — — 49Ah — Unimplemented — — 49Bh — Unimplemented — — 49Ch — Unimplemented — — 49Dh — Unimplemented — — 49Eh — Unimplemented — — 49Fh — Unimplemented — — TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Unimplemented, read as ‘1’. |
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