PIC12LC671 datasheet(7/130 Pages) MICROCHIP

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 1997-2013 Microchip Technology Inc.

DS30561C-page 7

PIC12C67X

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC12C67X family can be

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC12C67X uses a Harvard architecture, in which

program and data are accessed from separate memo-

ries using separate buses. This improves bandwidth

over traditional von Neumann architecture in which pro-

gram and data are fetched from the same memory

using the same bus. Separating program and data

buses also allow instructions to be sized differently than

the 8-bit wide data word. Instruction opcodes are 14-

bits wide making it possible to have all single word

instructions. A 14-bit wide program memory access

bus fetches a 14-bit instruction in a single instruction

cycle. A two-stage pipeline overlaps fetch and execu-

tion of instructions (Example 3-1). Consequently, all

instructions (35) execute in a single cycle (200 ns @ 20

MHz) except for program branches.

The table below lists program memory (EPROM), data

memory (RAM), and non-volatile memory (EEPROM)

for each PIC12C67X device.

Device

Program

Memory

RAM Data

Memory

EEPROM

Data

Memory

PIC12C671

1K x 14

128 x 8

—

PIC12C672

2K x 14

128 x 8

—

PIC12CE673

1K x 14

128 x 8

16x8

PIC12CE674

2K x 14

128 x 8

16x8

The PIC12C67X can directly or indirectly address its

ters, including the program counter, are mapped in the

data memory. The PIC12C67X has an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make programming with the

PIC12C67X simple yet efficient. In addition, the learn-

ing curve is reduced significantly.

PIC12C67X devices contain an 8-bit ALU and working

It performs arithmetic and Boolean functions between

the data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the working register (W register). The

other operand is a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow bit and a digit borrow out bit,

respectively, in subtraction. See the SUBLW and SUBWF

instructions for examples.

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