PIC16F84A datasheet(13/90 Pages) MICROCHIP

13 / 90 page

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DS35007C-page 13

PIC16F84A

3.0

DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register file space. Instead

it is indirectly addressed through the Special Function

Registers. There are four SFRs used to read and write

this memory. These registers are:

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. PIC16F84A devices have 64 bytes of

data EEPROM with an address range from 0h to 3Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write-

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC specifications for

exact limits.

When the device is code protected, the CPU may

continue to read and write the data EEPROM memory.

The device programmer can no longer access

this memory.

Additional information on the Data EEPROM is avail-

able in the PIC® Mid-Range Reference Manual

(DS33023).

EECON1 REGISTER (ADDRESS 88h)

U-0

R/W-0

R/W-x

R/W-0

R/S-0

—

EEIF

WRERR

WREN

bit 7

bit 0

bit 7-5

Unimplemented: Read as '0'

bit 4

EEIF: EEPROM Write Operation Interrupt Flag bit

= The write operation completed (must be cleared in software)

= The write operation is not complete or has not been started

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR Reset or any WDT Reset during normal operation)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the EEPROM

bit 1

WR: Write Control bit

= Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not

cleared) in software.

= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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