LCMXO2-256ZE-1TG100C datasheet(6/106 Pages) LATTICE

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2-2

Architecture

MachXO2 Family Data Sheet

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen-

sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are

located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic,

RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports

operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing

channel resources. The place and route software tool automatically allocates these routing resources.

In the MachXO2 family, the number of sysIO banks varies by device. There are different types of I/O buffers on the

different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast

memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as

RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT

usage.

The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2-

640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The

PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase rela-

tionships of the clocks.

MachXO2 devices provide commonly used hardened functions such as SPI controller, I

2C controller and timer/

counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened

functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also

be accessed through the SPI, I

2C and JTAG ports.

Every device in the family has a JTAG port that supports programming and configuration of the device as well as

access to the user logic. The MachXO2 devices are available for operation from 3.3V, 2.5V and 1.2V power sup-

plies, providing easy integration into the overall system.

PFU Blocks

The core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic,

distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0

to 3 as shown in Figure 2-3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs

associated with each PFU block.

Figure 2-3. PFU Block Diagram

Slice 0

LUT4 &

CARRY

LUT4 &

CARRY

FF/

Latch

FCIN

FCO

FF/

Latch

Slice 1

LUT4 &

CARRY

LUT4 &

CARRY

Slice 2

LUT4 &

CARRY

LUT4 &

CARRY

From

Routing

Slice 3

LUT4 &

CARRY

LUT4 &

CARRY

FF/

Latch

FF/

Latch

FF/

Latch

FF/

Latch

FF/

Latch

FF/

Latch

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