LCMXO2-256ZE-1MG132C datasheet(13/106 Pages) LATTICE

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2-9

Architecture

MachXO2 Family Data Sheet

Table 2-4 provides signal descriptions of the PLL block.

sysMEM Embedded Block RAM Memory

The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a

9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes

including data buffering, PROM for the soft processor and FIFO.

sysMEM Memory Block

The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be

used in a variety of depths and widths as shown in Table 2-5.

Table 2-4. PLL Signal Descriptions

Port Name

I/O

Description

CLKI

Input clock to PLL

CLKFB

Feedback clock

PHASESEL[1:0]

Select which output is affected by Dynamic Phase adjustment ports

PHASEDIR

Dynamic Phase adjustment direction

PHASESTEP

Dynamic Phase step – toggle shifts VCO phase adjust by one step.

CLKOP

Primary PLL output clock (with phase shift adjustment)

CLKOS

Secondary PLL output clock (with phase shift adjust)

CLKOS2

Secondary PLL output clock2 (with phase shift adjust)

CLKOS3

Secondary PLL output clock3 (with phase shift adjust)

LOCK

PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed-

back signals.

DPHSRC

Dynamic Phase source – ports or

WISHBONE is active

STDBY

Standby signal to power down the PLL

RST

PLL reset without resetting the M-divider. Active high reset.

RESETM

PLL reset - includes resetting the M-divider. Active high reset.

RESETC

Reset for CLKOS2 output divider only. Active high reset.

RESETD

Reset for CLKOS3 output divider only. Active high reset.

ENCLKOP

Enable PLL output CLKOP

ENCLKOS

Enable PLL output CLKOS when port is active

ENCLKOS2

Enable PLL output CLKOS2 when port is active

ENCLKOS3

Enable PLL output CLKOS3 when port is active

PLLCLK

PLL data bus clock input signal

PLLRST

PLL data bus reset. This resets only the data bus not any register values.

PLLSTB

PLL data bus strobe signal

PLLWE

PLL data bus write enable signal

PLLADDR [4:0]

PLL data bus address

PLLDATI [7:0]

PLL data bus data input

PLLDATO [7:0]

PLL data bus data output

PLLACK

PLL data bus acknowledge signal

LCMXO2-256ZE-1MG132C 数据表(PDF) 13 Page - Lattice Semiconductor

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