LCMXO2-256ZE-2MG132C datasheet(4/106 Pages) LATTICE

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Introduction

MachXO2 Family Data Sheet

and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low

static power for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)

devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Sim-

ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC

devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE

and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage

all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space

saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range

of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-

bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-

down and bus-keeper features are controllable on a “per-pin” basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may

be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-

ilar state machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the

JTAG test access port or through the I

2C port. Additionally, MachXO2 devices support dual-boot capability (using

external Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and

route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into

the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of

reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft

core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-

ing their productivity.

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