AD5241BRUZ1M-R7 datasheet(4/20 Pages) AD

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AD5241/AD5242

Rev. C | Page 4 of 20

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

DYNAMIC CHARACTERISTICS5, 7, 8

−3 dB Bandwidth

BW_10 kΩ

RAB = 10 kΩ, code = 0x80

650

kHz

BW_100 kΩ

RAB = 100 kΩ, code = 0x80

kHz

BW_1 MΩ

RAB = 1 MΩ, code = 0x80

kHz

Total Harmonic Distortion

THDW

VA = 1 V rms + 2 V dc,

VB = 2 V dc, f = 1 kHz

0.005

VW Settling Time

VA = VDD, VB = 0 V, ± 1 LSB

error band, RAB = 10 kΩ

μs

Resistor Noise Voltage

eN_WB

RWB = 5 kΩ, f = 1 kHz

nV√Hz

INTERFACE TIMING CHARACTERISTICS

(APPLIES TO ALL PARTS5, 9)

SCL Clock Frequency

fSCL

400

kHz

Bus Free Time Between Stop and Start, tBUF

1.3

μs

Hold Time (Repeated Start), tHD; STA

After this period, the first

clock pulse is generated

600

Low Period of SCL Clock, tLOW

1.3

μs

High Period of SCL Clock, tHIGH

0.6

μs

Setup Time for Repeated Start Condition, tSU;STA

600

Data Hold Time, tHD; DAT

900

Data Setup Time, tSU; DAT

100

Rise Time of Both SDA and SCL Signals, tR

300

Fall Time of Both SDA and SCL Signals, tF

300

Setup Time for Stop Condition, tSU; STO

t10

1 Typicals represent average readings at 25°C, VDD = 5 V.

2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.

3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.

4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

5 Guaranteed by design, not subject to production test.

6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

8 All dynamic characteristics use VDD = 5 V.

9 See timing diagram in Figure 3 for location of measured values.

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