AD7607 datasheet(25/32 Pages) AD

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Data Sheet

AD7607

Rev. B | Page 25 of 32

Figure 42 shows a read of eight simultaneous conversion results

using two DOUT lines on the AD7607. In this case, a 56 SCLK

transfer is used to access data from the AD7607, and CS is held

low to frame the entire 56 SCLK cycles. Data can also be clocked

out using just one DOUT line; in which case, it is recommended

that DOUTA be used to access all conversion data because the

channel data is output in ascending order. For the AD7607 to

access all eight conversion results on one DOUT line, a total of

112 SCLK cycles are required. These 112 SCLK cycles can be

framed by one CS signal, or each group of 14 SCLK cycles can be

individually framed by the CS signal. The disadvantage of using

just one DOUT line is that the throughput rate is reduced

if reading occurs after conversion. The unused DOUT line should

be left unconnected in serial mode. If DOUTB is to be used as a

single DOUT line, the channel results are output in the following

order: V5, V6, V7, V8, V1, V2, V3, and V4; however, the

FRSTDATA indicator returns low after V5 is read on DOUTB.

Figure 6 shows the timing diagram for reading one channel of

data, framed by the CS signal, from the AD7607 in serial mode.

The SCLK input signal provides the clock source for the serial

read operation. The CS goes low to access the data from the

AD7607. The falling edge of CS takes the bus out of three-state

and clocks out the MSB of the 14-bit conversion result. This

MSB is valid on the first falling edge of the SCLK after the CS

falling edge.

The subsequent 13 data bits are clocked out of the AD7607 on the

SCLK rising edge. Data is valid on the SCLK falling edge. To access

each conversion result, 14 clock cycles must be provided.

The FRSTDATA output signal indicates when the first channel,

V1, is being read back. When the CS input is high, the FRSTDATA

output pin is in three-state. In serial mode, the falling edge of CS

takes FRSTDATA out of three-state and sets the FRSTDATA pin

high, indicating that the result from V1 is available on the DOUTA

output data line. The FRSTDATA output returns to a logic low

following the 14th SCLK falling edge. If all channels are read on

DOUTB, the FRSTDATA output does not go high when V1 is output

on this serial data output pin. It goes high only when V1 is available

on DOUTA (and this is when V5 is available on DOUTB).

READING DURING CONVERSION

Data can be read from the AD7607 while BUSY is high and the

conversions are in progress. This has little effect the performance

of the converter, and it allows a faster throughput rate to be

achieved. A parallel, parallel byte, or serial read can be performed

during conversions and when oversampling is or is not enabled.

Figure 3 shows the timing diagram for reading while BUSY is

high in parallel or serial mode. Reading during conversions

allows the full throughput rate to be achieved when using the

serial interface with VDRIVE above 3.3 V.

Data can be read from the AD7607 at any time other than on

the falling edge of BUSY because this is when the output data

registers get updated with the new conversion data. Time t6, as

outlined in Table 3, should be observed in this condition.

SCLK

DOUTA

DOUTB

Figure 42. Serial Interface with Two DOUT Lines

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