AD9736BBC datasheet(41/72 Pages) AD

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AD9734/AD9735/AD9736

Rev. A | Page 41 of 72

To find the leading edge of the data cycle, increment the

measured setup delay until the check bit goes low. To find the

trailing edge, increment the measured hold delay (MHD) until

check goes low. Always set MHD = 0 when incrementing MSD

and vice versa.

The incremental units of SD, MSD, and MHD are in units of real

time, not fractions of a clock cycle. The nominal step size is 80 ps.

OPERATING THE LVDS CONTROLLER IN

MANUAL MODE VIA THE SPI PORT

The manual operation of the LVDS controller allows the user to

step through both the setup and hold delays to calculate the

optimal sampling delay (that is, the center of the data eye).

With SD<3:0> and MHD<3:0> set to 0, increment the setup time

delay (MSD<3:0>, Reg. 4, Bits 7:4) until the check bit (Reg. 5,

Bit 0) goes low and record this value. This locates the leading

DATACLK_IN (and data) transition, as shown in Figure 80.

With SD<3:0> and MSD<3:0> set to 0, increment the hold time

delay (MHD<3:0>, Reg. 4, Bits 3:0) until the check bit (Reg. 5,

Bit 0) goes low and record this value. This locates the trailing

DATACLK_IN (and DB<13:0>) transition, as shown in Figure

81.

Once both DATACLK_IN edges are located, the sample delay

(SD<3:0>, Reg. 5, Bits 7:4) must be updated by

Sample Delay = (MHD − MSD)/2

After updating SD<3:0>, verify that the sampling signal is in the

middle of the valid data window by adjusting both MHD and

MSD with the new sample delay until the check bit goes low.

The new MHD and MSD values should be equal to or within

one unit delay if SD<3:0> was set correctly.

MHD and MSD may not be equal to or within one unit delay if

the external clock jitter and noise exceeds the internal delay

resolution. Differences of 2, 3, or more are possible and can

require more filtering to provide stable operation.

The sample delay calibration should be performed prior to

enabling surveillance mode or auto mode.

SETUP TIME (

tS)

SAMPLE DELAY

MSD<3:0> = 0 1 2 3 4 5

CSS SAMPLE DCS

CHECK = 1

SD<3:0>

DB<13:0>

DATACLK_IN

CSS WITH

MHD<3:0> = 0

DSC DELAYED

BY MSD<3:0>

Figure 80. Setup Delay Measurement

SETUP TIME (

tS)

HOLD TIME (

tH)

SAMPLE DELAY

CSS SAMPLE DCS

CHECK = 1 1 1 1 1 0

CHECK = 1

SD<3:0>

MSD<3:0> = 0 1 2 3 4 5

DB<13:0>

DATACLK_IN

CSS WITH

MHD<3:0> = 0

DSC DELAYED

BY MSD<3:0> = 0

Figure 81. Hold Delay Measurement

OPERATING THE LVDS CONTROLLER IN

SURVEILLANCE AND AUTO MODE

In surveillance mode, the controller searches for the edges of

the data eye in the same manner as in the manual mode of

operation and triggers an interrupt if the clock sampling signal

(CSS) has moved more than the threshold value set by

LTRH<1:0> (Reg. 6, Bits 1:0).

There is an internal filter that averages the setup and hold time

measurements to filter out noise and glitches on the clock lines.

Average Value = (MHD – MSD)/2

New Average = Average Value + (Δ Average/2 ^ LFLT<3:0>)

If an accumulating error in the average value causes it to exceed

the threshold value (LTHR<1:0>), an interrupt is issued.

The maximum allowable value for LFLT<3:0> is 12. If

LFLT<3:0> is too small, clock jitter and noise can cause erratic

behavior. In most cases, LFLT can be set to the maximum value.

In surveillance mode, the ideal sampling point should first be

found using manual mode and then applied to the sample delay

registers. Set the threshold and filter values depending on how

far the CSS signal is allowed to drift before an interrupt occurs.

Then, set the surveillance bit high (Reg. 6, Bit 7) and monitor

the interrupt signal either via the SPI port (Reg. 1, Bit 7) or the

IRQ pin.

In auto mode, follow the same steps to set up the sample delay,

threshold, and filter length. To run the controller in auto mode,

both the LAUTO (Reg. 6, Bit 6) and LSURV (Reg. 6, Bit 7) bits

need to be set to 1. In auto mode, the LVDS interrupt should be

set low (Reg. 1, Bit 3) to allow the sample delay to be automati-

cally updated if the threshold value is exceeded.

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