MCP795W2X datasheet(8/54 Pages) MICROCHIP

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MCP795W1X/MCP795W2X

DS22280C-page 8

Preliminary

 2011-2012 Microchip Technology Inc.

3.0

SPI BUS OPERATION

The MCP795WXX is designed to interface directly with

the Serial Peripheral Interface (SPI) port of many of

today’s popular microcontroller families, including

Microchip’s PIC® microcontrollers. It may also interface

with microcontrollers that do not have a built-in SPI port

by using discrete I/O lines programmed properly in

software to match the SPI protocol.

The MCP795WXX contains an 8-bit instruction register.

The device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low for the entire operation.

Table 3-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSb first, LSb last.

Data (SI) is sampled on the first rising edge of SCK

after CS goes low.

TABLE 3-1:

INSTRUCTION SET SUMMARY

3.1

Read Sequence

The device is selected by pulling CS low. The various

8-bit read instructions are transmitted to the

MCP795WXX followed by an 8-bit address. See

Figure 3-1 for more details.

After the correct instruction and address are sent, the

data stored in the memory at the selected address is

shifted out on the SO pin. Data stored in the memory at

the next address can be read sequentially by

continuing to provide clock pulses to the slave. The

internal Address Pointer automatically increments to

the next higher address after each byte of data is

shifted out. When the highest address is reached, the

address counter rolls over to the first valid address

allowing the read cycle to be continued indefinitely. The

read operation is terminated by raising the CS pin

(Figure 1-1).

FIGURE 3-1:

EEREAD SEQUENCE

Instruction Name

Instruction Format

Description

EEREAD

0000 0011

Read data from EE memory array beginning at selected address

EEWRITE

0000 0010

Write data to EE memory array beginning at selected address

EEWRDI

0000 0100

Reset the write enable latch (disable write operations)

EEWREN

0000 0110

Set the write enable latch (enable write operations)

SRREAD

0000 0101

Read STATUS register

SRWRITE

0000 0001

Write STATUS register

READ

0001 0011

Read RTCC/SRAM array beginning at selected address

WRITE

0001 0010

Write RTCC/SRAM data to memory array beginning at selected

address

UNLOCK

0001 0100

Unlock ID Locations

IDWRITE

0011 0010

Write to the ID Locations

IDREAD

0011 0011

Read the ID Locations

CLRWDT

0100 0100

Clear Watchdog TImer

CLRRAM

0101 0100

Clear RAM Location to ‘0’

SCK

23456

789 10 11

A7 A6 A5 A4

A1 A0

76543210

Data Out

High-Impedance

A3 A2

Address Byte

12 13 14 15 16 17 18 19 20 21 22 23

Instruction

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