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ADP160ACBZ-1.8-R7 数据表(PDF) 14 Page - Analog Devices

部件名 ADP160ACBZ-1.8-R7
功能描述  Ultralow Quiescent Current, 150 mA, CMOS Linear Regulators
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP160ACBZ-1.8-R7 数据表(HTML) 14 Page - Analog Devices

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ADP160/ADP161/ADP162/ADP163
Data Sheet
Rev. G | Page 14 of 24
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP16x are designed for operation with small, space-
saving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken with regard to the
effective series resistance (ESR) value. The ESR of the output
capacitor affects stability of the LDO control loop. A minimum
of 1 µF capacitance with an ESR of 1 Ω or less is recommended
to ensure stability of the ADP16x. Transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP16x to large changes in load current. Figure 34
and Figure 35 show the transient responses for output
capacitance values of 1 µF and 10 µF, respectively.
CH1 100mA Ω CH2 200mV
M200µs
A CH1
62mA
T 10.40%
1
2
T
LOAD CURRENT
VOUT
Figure 34. Output Transient Response, COUT = 1 µF,
CH1 = Load Current, CH2 = VOUT
CH1 100mA Ω CH2 200mV
M200µs
A CH1
74mA
T 10.00%
1
2
T
LOAD CURRENT
VOUT
Figure 35. Output Transient Response, COUT = 10 µF,
CH1 = Load Current, CH2 = VOUT
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the circuit
sensitivity to the printed circuit board (PCB) layout, especially
when long input traces or high source impedance are encountered.
If greater than 1 µF of output capacitance is required, the input
capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP16x, as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufactured
with a variety of dielectrics, each with different behavior over
temperature and applied voltage. Capacitors must have a dielectric
adequate to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended. Y5V
and Z5U dielectrics are not recommended due to their poor
temperature and dc bias characteristics.
Figure 36 depicts the capacitance vs. voltage bias characteristic
of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
VOLTAGE
Figure 36. Capacitance vs. Voltage Characteristic
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 0.94 µF at 1.8 V, as shown in Figure 36.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 µF
Therefore, the capacitor chosen in this example meets
the minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.



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