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HT66F30 数据表(PDF) 13 Page - Holtek Semiconductor Inc

部件名 HT66F30
功能描述  Enhanced A/D Flash Type 8-Bit MCU with EEPROM
PDF  298 Pages
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制造商  HOLTEK [Holtek Semiconductor Inc]
网页  http://www.holtek.com
标志 HOLTEK - Holtek Semiconductor Inc

HT66F30 数据表(HTML) 13 Page - Holtek Semiconductor Inc

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Rev. 1.90
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Rev. 1.90
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pin Assignment
HT 66 F2 0
16 D IP -A /N SO P- A/ SSO P- A
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PA 1/ TP 1 _0/ AN 1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/S DA /A N6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
PA 1/ TP 1 _0/ AN 1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/S DA /A N6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PC 2/ PC K/ C1 +/ SC OM 2
PC 3/ PI NT /C 1- /S CO M3
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
PC 1/ SC OM 1
PC 0/ TP 1_1/ SC OM 0
HT 66 F2 0
20 D IP -A /S OP -A /S SO P- A
HT 66 F3 0
16 D IP -A /N SO P- A/ SSO P- A
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PA 1/ TP 1A /A N1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/S DA /A N6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
PA 1/ TP 1A /A N1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/ SD A/ AN 6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PC 2/ PC K/ C1 +
PC 3/ PI NT /C 1-
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
PC 1/ TP 1B _1 /[ SD O] /S CO M1
PC 0/ TP 1B _0 /[S DI /S DA ]/ SC OM 0
HT 66 F3 0
20 D IP -A /S OP -A /S SO P- A
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
HT 66 F3 0
24 S KD IP -A /S OP -A / SSO P- A
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
PC 1/ TP 1B _1 /[ SD O] /S CO M1
PC 0/ TP 1B _0 /[S DI /S DA ]/ SC OM 0
PC 7/ [S CK /S CL ]/ SC OM 3
PC 6/ [S CS ]/ SC OM 2
PA 1/ TP 1A /A N1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/S DA /A N6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PC 2/ PC K/ C1 +
PC 3/ PI NT /C 1-
PC 4/ [P IN T]
PC 5/ TP 0_1/ [P CK ]
PA 1/ TP 1A /A N1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/S DA /A N6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PC 2/ TC K2 /P CK /C 1+
PC 3/ PI NT /T P 2_0/ C1 -
PC 4 /[IN T0 ]/[ PI NT ]/ TP 2_1
PC 5 /[IN T1 ]/T P 0_1/ TP 1B _2/ [P CK ]
PD 0 /[T CK 2] /[ SC S]
PD 1 /[T P 2_0] /[S DO ]/[S CK /S CL ]
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HT 66 F4 0
28 S KD IP -A /S OP -A /S SO P- A
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
PC 1/ TP 1B _1 /S CO M1
PC 0/ TP 1B _0 /S CO M0
PC 7 /[T P1 A ]/S CO M3
PC 6 /[T P 0_0] /S CO M2
PD 3 /[T CK 1] /[ SD O]
PD 2 /[T CK 0 ]/[ SD I/S DA ]
HT 66 F4 0
24 S KD IP -A /S OP -A / SSO P- A
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
PA 0/ C0 X/ TP 0_0 /A N0
VSS&AVSS
PB 4/ XT 2
PB 3/ XT 1
PB 2/ OS C2
PB 1/ OS C1
VD D& AV DD
PB 0/ RE S
PC 1/ TP 1B _1 /S CO M1
PC 0/ TP 1B _0 /S CO M0
PC 7 /[T P1 A] /S CO M3
PC 6/ [T P 0_0] /S CO M2
PA 1/ TP 1A /A N1
PA 2/ TC K0 /C 0+ /A N2
PA 3/ IN T0 /C 0- /A N3
PA 4/ IN T1 /T CK 1/ AN 4
PA 5/ C1 X/ SD O/ AN 5
PA 6/ SD I/ SD A/ AN 6
PA 7/ SC K/ SC L/ AN 7
PB 5/ SC S/ VR EF
PC 2/ TC K2 /P CK /C 1+
PC 3/ PI NT /T P 2_0/ C1 -
PC 4/ [I NT 0 ]/[P IN T] /T P 2_1
PC 5/ [I NT 1 ]/T P 0_1/ TP 1B _2/ [P CK ]
Note:1.Bracketedpinnamesindicatenon-defaultpinoutremappinglocations.
2.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,itspinnamesattherightsideofthe
"/"signcanbeusedforhigherpriority.
3.VDD&AVDDmeanstheVDDandAVDDarethedoublebonding.



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