TLK1501

0.6 TO 1.5 GBPS TRANSCEIVER

SLLS428F − JUNE 2000 − REVISED JANUARY 2004

7

POST OFFICE BOX 655303

detailed description

transmit interface

The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of the GTX_CLK.

The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential high-speed

I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times, creating a

bit clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising

and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock. Data is

transmitted LSB (TXD0) first. The transmitter also inserts commas at the beginning of the transmission for byte

synchronization.

transmit data bus

The transmit bus interface accepts 16-bit single-ended TTL parallel data at the TXD[0:15] terminals. Data is

valid on the rising edge of the GTX_CLK when the TX_EN is asserted high and the TX_ER is deasserted low.

The GTX_CLK is used as the word clock. The data, enable, and clock signals must be properly aligned as shown

in Figure 2. Detailed timing information can be found in the electrical characteristics table.

GTX_CLK

TXDn, TX_EN, TX_ER

tsu

th

Figure 2. Transmit Timing Waveform