IP1837 datasheet(34/40 Pages) IRF

34 / 40 page

iP1837

Highly Integrated 35A Single‐input Voltage,

Synchronous Buck Regulator

March 5, 2012 | V1.26

97600

LAYOUT CONSIDERATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect noise

pickup and can cause a good design to perform with less

than expected results.

Make all the connections for the power components in

the top layer with wide, copper filled areas or polygons.

In general, it is desirable to make proper use of power

planes and polygons for power distribution and heat

dissipation.

The inductor, output capacitors and the iP1837 should be

as close to each other as possible. This helps to reduce the

EMI radiated by the power traces due to the high switching

currents through them.

The input capacitors should be placed as close as possible

to the PGnd pad. The connection of the Vin pad to the Vin

power polygon should be low impedance, using several

vias in parallel. The layout must ensure minimum length

ground path and enough copper for input and output

capacitors with a direct connection.

The iP1837 has a local power ground pad called Bias Gnd

(pin 12) for bypassing Vcc or PVcc supplies. The analog or

signal ground, LGnd, is used as a separate control circuit

ground to which all signals are referenced. The analog

ground polygon should be connected to BiasGnd through

a single point connection using a 0 ohm resistor, at a

location away from noise sources. The PGnd pad (Pin 3)

should be connected to system power Ground.

In order to minimize coupling switching noise into other

layers, the area of the switch node copper should be kept

small. It is also advisable to keep the switch node copper

localized to the top layer.

The critical bypass components such as capacitors for

Vcc should be close to their respective pins. It is important

to place the feedback components including feedback

resistors and compensation components close to Fb and

Comp pins.

A pair of sense traces running very close to each other and

away from any noise sources should be used to implement

true differential remote sensing of the voltage.

If remote sense is not used, the output voltage sense trace

used for feedback should be tapped from a low impedance

point such as directly from an output capacitor.

The iPOWiR package is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 6‐layers PCB. Figures 35a‐f illustrates the

implementation of the layout guidelines outlined above,

on the IRDC1837 6 layer demoboard.

Figure 35a: IRDC1837 demoboard layout considerations – Top Layer

Enough copper

& minimum length

ground path between

Input and Output

All bypass caps

(Marked in Cyan) should be

placed as close as possible

to their connecting pins

BiasGnd

Single Point Connection

of AGND and BiasGnd

Resistors Rt (marked in Brown)

should be placed as close as

possible to their pins

Compensation parts

(Marked in dark blue)

should be placed as close as

possible to the Comp pin

Switch node should have small area and

should be localized to Top layer

Optional on board

load transient circuit:

Not Critical

Switch node should

have small area and

should be localized

to Top layer

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