DocID4997 Rev 13

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M93C86xx M93C76xx M93C66xx M93C56xx M93C46xx

READY/BUSY status

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READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL

instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.

becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write

cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)

indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)

remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is

decoded.

7

Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).