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STM6718 数据表(PDF) 5 Page - STMicroelectronics |
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STM6718 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 30 page ![]() STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description Doc ID 11469 Rev 8 5/30 1 Description The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/low- supply current processor (micro or DSP) supervisors, designed to monitor two (or three) system power supply voltages. They are targeted at applications such as set-top boxes (STBs), portable, battery-powered systems, networking, and communication systems. All device options have a push-button-type manual reset input (MR). The STM6777/78/79/80 also includes an option which enables the user to delay the start of the manual reset process from 6 µs (MRC pin left open) or more with external capacitor. The delay is implemented by connecting the appropriately sized capacitor between the MRC pin and VSS (typical 4 s delay with a 3.3 µF capacitor, see Table 7 on page 21). Two of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable, factory-trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an externally adjustable RSTIN threshold (0.626 V internal reference). If any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted, RST is maintained at low for a minimum delay period (trec) after ALL supplies rise above their respective thresholds and MR returns to high. These devices are guaranteed to be in the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8 V. These devices are available in standard 5-pin or 6-pin SOT23 packages (see Table 1 on page 1). |
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