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OMAP3530ECUS72 数据表(PDF) 7 Page - Texas Instruments |
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OMAP3530ECUS72 数据表(HTML) 7 Page - Texas Instruments |
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7 / 264 page  1.3 Functional Block Diagram IVA 2.2Subsystem TMS320DM64x+DSP ImagingVideoand AudioProcessor 32K/32KL1$ 48KL1DRAM 64KL2$ 32KL2RAM 16KL2ROM VideoHardware Accelerators 64 32 Async 64 32 64 64 Async 64 64 L2$ 256K MPU Subsystem ARMCortex- A8 TM Core 16K/16KL1$ POWERVR SGX Graphics Accelerator (3530only) TM 32 32 32 Channel System DMA 32 32 Parallel TV Amp LCDPanel CVBS or S-Video DualOutput3-Layer DisplayProcessor (1xGraphics,2xVideo) TemporalDithering SDTV → QCIFSupport 32 Camera ISP Image Capture Hardware Image Pipeline and Preview Camera (Parallel) 64 HSUSB Host (with USB TTL) HS USB OTG 32 L3InterconnectNetwork-Hierarchial,Performance,andPowerDriven 64K On-Chip RAM 2KB Public/ 62KB Secure 32 112K On-Chip ROM 80KB Secure/ 32KB BOOT 32 SMS: SDRAM Memory Scheduler/ Rotation 64 SDRC: SDRAM Memory Controller L4Interconnect 32 System Controls PRCM 2xSmartReflex TM Control Module External Peripherals Interfaces Peripherals: 3xUART,3xHigh-SpeedI2C, 5xMcBSP (2xwithSidetone/AudioBuffer) 4xMcSPI,6xGPIO, 3xHigh-SpeedMMC/SDIO, HDQ/1Wire, 2xMailboxes 12xGPTimers,2xWDT, 32KSyncTimer GPMC: General Purpose Memory Controller NAND/ NOR Flash, SRAM 32 Emulation Debug:SDTI,ETM,JTAG, Coresight TM DAP Externaland StackedMemories 32 OMAP ApplicationsProcessor OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Figure 1-1 shows the functional block diagram of the OMAP3530/25 Applications Processor. Figure 1-1. OMAP3530/25 Functional Block Diagram Submit Documentation Feedback OMAP3530/25 Applications Processor 7 |
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