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STPMS2L-PUR 数据表(PDF) 22 Page - STMicroelectronics

部件名 STPMS2L-PUR
功能描述  Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA
PDF  33 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPMS2L-PUR 数据表(HTML) 22 Page - STMicroelectronics

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Theory of operation
STPMS2
22/33
Doc ID 16525 Rev 3
In this way it is possible to access 128 different combinations, which are controlled through
pins MS0, MS1, MS2 and MS3.
MS0 sets the operating mode and amplifier gain selection as described in Table 8.
For the STPMS2L:
MS0=GND or CLK to select LPR (low precision); fCLK = 1 MHz is the typical input clock
frequency and low power mode is selected.
MS0=NCLK or VCC to select HPR (high precision): fCLK = 2 MHz is the typical input
clock frequency and accuracy is enhanced.
For the STPMS2H, LPR mode is not used and the settings should be chosen between
MS0=NCLK or VCC. In this case, fCLK = 4 MHz is typical.
The relative gain of the current channel is selectable between 2 or 16, which defines the
maximum differential voltage on the current channel to ± 300 mV or ± 37.5 mV, respectively.
The voltage channel gain setting is fixed at 2, which defines the maximum differential
voltage on the voltage channel inputs to ± 300 mV.
MS1 defines the temperature compensation (TC) curve of the internal voltage reference of
the STPMS2L, as described in Table 9. This bootstrap function is not used with the
STPMS2H. The temperature-compensated reference voltage generator produces VREF =
1.23 V. This generator is implemented as a band gap generator, whose temperature
compensation curve can be selected through the MS1 configuration pin.
MS2 defines the outputs of the device:
The STPMS2 sends to the DAT and DATn pins the sigma-delta streams synchronous to the
CLK signal. The output mode can be configured according to Table 10 as follows:
The output current channel's sigma-delta stream on DAT and the voltage channel's
sigma-delta stream on DATn
Output multiplexed signals, so when CLK = 0, the current channel output sigma-delta
value is set on the DAT pin, and when CLK = 1, the voltage channel output sigma-delta
value is set on the DAT pin. The DATn pin tracks DAT, so DATn = ~DAT.
Output current channel's sigma-delta stream on DAT and the current channel's sigma-
delta stream negated on DATn
Table 8.
Precision mode and input amplifier gain selection
MS0
Mode
Description
GND
0
LPR, amplifier GAIN selection g3 = 16
CLK
1
LPR, amplifier GAIN selection g0 = 2
NCLK
2
HPR, amplifier GAIN selection g0 = 2
VCC
3
HPR, amplifier GAIN selection g3 = 16
Table 9.
TC of the band-gap reference
MS1
Mode
Description
GND
0
TC = 60 ppm/°C
CLK
1
Flattest TC = +30 ppm/°C
NCLK
2
TC = +160 ppm/°C
VCC
3
TC = -160 ppm/°C



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