数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CY62156ESL 数据表(PDF) 7 Page - Cypress Semiconductor

部件名 CY62156ESL
功能描述  8-Mbit (512 K x 16) Static RAM
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY62156ESL 数据表(HTML) 7 Page - Cypress Semiconductor

Back Button CY62156ESL Datasheet HTML 3Page - Cypress Semiconductor CY62156ESL Datasheet HTML 4Page - Cypress Semiconductor CY62156ESL Datasheet HTML 5Page - Cypress Semiconductor CY62156ESL Datasheet HTML 6Page - Cypress Semiconductor CY62156ESL Datasheet HTML 7Page - Cypress Semiconductor CY62156ESL Datasheet HTML 8Page - Cypress Semiconductor CY62156ESL Datasheet HTML 9Page - Cypress Semiconductor CY62156ESL Datasheet HTML 10Page - Cypress Semiconductor CY62156ESL Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 16 page
background image
CY62156ESL MoBL®
Document Number: 001-54995 Rev. *D
Page 7 of 16
Switching Characteristics
Over the Operating Range
Parameter [13]
Description
45 ns
Unit
Min
Max
Read Cycle
tRC
Read Cycle Time
45
ns
tAA
Address to Data Valid
45
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
ns
tDOE
OE LOW to Data Valid
22
ns
tLZOE
OE LOW to Low Z[14]
5
ns
tHZOE
OE HIGH to High Z[14, 15]
18
ns
tLZCE
CE1 LOW and CE2 HIGH to Low Z[14]
10
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z[14, 15]
18
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
0
ns
tPD
CE1 HIGH and CE2 LOW to Power Down
45
ns
tDBE
BLE/BHE LOW to Data Valid
22
ns
tLZBE
BLE/BHE LOW to Low Z[14]
5
ns
tHZBE
BLE/BHE HIGH to High Z[14, 15]
18
ns
Write Cycle[16]
tWC
Write Cycle Time
45
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z[14, 15]
18
ns
tLZWE
WE HIGH to Low Z[14]
10
ns
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com