FX3 datasheet(13/45 Pages) CYPRESS

13 / 45 page

CYUSB301X

Document Number: 001-52136 Rev. *N

Page 13 of 45

Configuration Options

Configuration options are available for specific usage models.

Contact Cypress Applications or Marketing for details.

Digital I/Os

FX3 has internal firmware-controlled pull-up or pull-down

resistors on all digital I/O pins. An internal 50-k

 resistor pulls

the pins high, while an internal 10-k

 resistor pulls the pins low

to prevent them from floating. The I/O pins may have the

following states:

■ Tristated (High-Z)

■ Weak pull-up (via internal 50 k)

■ Pull-down (via internal 10 k)

■ Hold (I/O hold its value) when in low-power modes

■ The JTAG TDI, TMC, and TRST# signals have fixed 50-k

internal pull-ups, and the TCK signal has a fixed 10-k



pull-down resistor.

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured separately for each interface.

GPIOs

EZ-USB enables a flexible pin configuration both on the GPIF II

and the serial peripheral interfaces. Any unused control pins

(except CTL[15]) on the GPIF II interface can be used as GPIOs.

Similarly, any unused pins on the serial peripheral interfaces may

be configured as GPIOs. See Pin Configurations for pin

configuration options.

All GPIF II and GPIO pins support an external load of up to 16 pF

for every pin.

EMI

FX3 meets EMI requirements outlined by FCC 15B (USA) and

EN55022 (Europe) for consumer electronics. FX3 can tolerate

reasonable EMI, conducted by the aggressor, outlined by these

specifications and continue to function as expected.

System-level ESD

FX3 has built-in ESD protection on the D+, D–, and GND pins on

the USB interface. The ESD protection levels provided on these

ports are:

■ ±2.2-KV human body model (HBM) based on JESD22-A114

Specification

■ ±6-KV contact discharge and ±8-KV air gap discharge based

on IEC61000-4-2 level 3A

■ ± 8-KV Contact Discharge and ±15-KV Air Gap Discharge

based on IEC61000-4-2 level 4C.

This protection ensures the device continues to function after

ESD events up to the levels stated in this section.

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-KV HBM internal ESD protection.

Pin Configurations

Figure 7. FX3 121-ball BGA Ball Map (Top View)

U3VSSQ

U3RXVDDQ

SSRXM

SSRXP

SSTXP

SSTXM

AVDD

VSS

VIO4

FSLC[0]

R_USB3

FSLC[1]

U3TXVDDQ

CVDDQ

AVSS

VSS

VDD

TRST#

GPIO[54]

GPIO[55]

VDD

GPIO[57]

RESET#

XTALIN

XTALOUT

R_USB2

OTG_ID

TDO

VIO5

GPIO[50]

GPIO[51]

GPIO[52]

GPIO[53]

GPIO[56]

CLKIN_32

CLKIN

VSS

I2C_GPIO[58] I2C_GPIO[59]

O[60]

GPIO[47]

VSS

VIO3

GPIO[49]

GPIO[48]

FSLC[2]

TDI

TMS

VDD

VBATT

VBUS

VIO2

GPIO[45]

GPIO[44]

GPIO[41]

GPIO[46]

TCK

GPIO[2]

GPIO[5]

GPIO[1]

GPIO[0]

VDD

VSS

GPIO[42]

GPIO[43]

GPIO[30]

GPIO[25]

GPIO[22]

GPIO[21]

GPIO[15]

GPIO[4]

GPIO[3]

VSS

VDD

GPIO[39]

GPIO[40]

GPIO[31]

GPIO[29]

GPIO[26]

GPIO[20]

GPIO[24]

GPIO[7]

GPIO[6]

VIO1

GPIO[38]

GPIO[36]

GPIO[37]

GPIO[34]

GPIO[28]

GPIO[16]

GPIO[19]

GPIO[14]

GPIO[9]

GPIO[8]

VDD

GPIO[35]

GPIO[33]

VSS

GPIO[27]

GPIO[23]

GPIO[18]

GPIO[17]

GPIO[13]

GPIO[12]

GPIO[10]

VSS

GPIO[32]

VDD

VSS

VDD

INT#

VIO1

GPIO[11]

VSS

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