AD679

REV. D

–4–

Parameter

Symbol

Min

Max

Unit

SC Delay

50

ns

Conversion Time

6.3

µs

Conversion Rate

1

7.8

µs

Convert Pulse Width

0.097

3.0

µs

Aperture Delay

520

ns

Status Delay

0

400

ns

Access Time

2, 3

10

100

ns

10

57

4

ns

Float Delay

5

10

80

ns

Output Delay

0ns

Format Setup

100

ns

OE Delay

20

ns

Read Pulse Width

195

ns

Conversion Delay

400

ns

EOCEN Delay

50

ns

NOTES

OE/EOCEN (0.8 V) to the time at which the

data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.

OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; C

OUT

= 10 pF.

Specifications subject to change without notice.

10%)

NOTES

CS DOES NOT AFFECT OPERATION.

SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.

2

EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-

STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.

Figure 1. Conversion Timing

Figure 2. Output Timing

NOTE

ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE

TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE

AND THE PULL-UP RESISTOR.

Figure 3. EOC Timing

TEST

ACCESS TIME HIGH Z TO LOGIC LOW 5V

100pF

FLOAT TIME LOGIC HIGH TO HIGH Z

0V

10pF

ACCESS TIME HIGH Z TO LOGIC HIGH

0V

100pF

FLOAT TIME LOGIC LOW TO HIGH Z

5V

10pF

Figure 4. Load Circuit for Bus Timing Specifications

TIMING SPECIFICATIONS