AD679

REV. D

–13–

AD679 to Analog Devices ADSP-2100A

Figure 12 demonstrates the AD679 interfaced to an ADSP-2100A.

With a clock frequency of 12.5 MHz, and instruction execution in

one 80 ns cycle, the digital signal processor supports the AD679

data memory interface with three hardware wait states.

The converter is configured to run asynchronously using a sam-

pling clock. The EOC output of the AD679 gets asserted at the

end of each conversion and causes an interrupt. Upon interrupt,

the ADSP-2100A immediately executes a data memory write

instruction, which asserts

HBE. In the following cycle, the pro-

cessor starts a data memory read (high byte read) by providing

an address on the DMA bus. The decoded address generates

OE for the converter. OE, together with logic and latch, is used

to force the ADSP-2100A into a one cycle wait state by generat-

ing DMACK. The read operation is thus started and completed

within two processor cycles (160 ns).

HBE is released during

high byte read. This allows the processor to read the lower byte

of data as soon as high byte read is complete. The low byte read

operation executes in a similar manner to the first and is com-

pleted during the next 160 ns.

Figure 12. AD679 to ADSP-2100A Interface