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74HC259DB 数据表(PDF) 13 Page - NXP Semiconductors |
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74HC259DB 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 23 page ![]() 74HC_HCT259 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 7 August 2012 13 of 22 NXP Semiconductors 74HC259; 74HCT259 8-bit addressable latch Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12. Load circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC259 VCC 6ns 15pF, 50 pF 1k open 74HCT259 3V 6ns 15pF, 50 pF 1k open |
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