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SC225KSIT 数据表(PDF) 12 Page - SEC Electronics Inc. |
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SC225KSIT 数据表(HTML) 12 Page - SEC Electronics Inc. |
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12 / 13 page ![]() SC225KSIT 120 kHz Bandwidth, High Voltage Isolation Current Sensor with Integrated Overcurrent Detection 12/13 2. When the FAULT pin voltage reaches approximately 2 V, the fault is latched, and an internal NMOS device pulls the FAULT pin voltage to approximately 0 V. The rate at which the FAULT pin slews downward (see [4] in the figure) is dependent on the external capacitor, COC, on the FAULT pin. 3. When the FAULT_EN pin is brought low, the FAULT pin starts resetting if no OC fault condition exists, and if FAULT_EN is low for a time period greater than tOCH. The internal NMOS pull-down turns off and an internal PMOS pullup turns on (see [7] if the OC fault condition still exists). 4. The slope, and thus the delay to latch the fault is controlled by the capacitor, COC, placed on the FAULT pin to ground. During this portion of the fault (when the FAULT pin is between VCC and 2 V), there is a 3 mA constant current sink, which discharges COC. The length of the fault delay, t is equal to: mA V V C t CC OC 3 ) 2 ( − × = where VCC is the device power supply voltage in volts, t is in seconds and COC is in Farads. This formula is valid for RPU equal to or greater than 330 kΩ. For lower-value resistors, the current flowing through the RPU resistor during a fault event, IPU , will be larger. Therefore, the current discharging the capacitor would be 3 mA – IPU and equation 1 may not be valid. 5. The FAULT pin did not reach the 2 V latch point before the OC fault condition cleared. Because of this, the fixed 3 mA current sink turns off, and the internal PMOS pull-up turns on to recharge COC through the FAULT pin. 6. This curve shows VCC charging external capacitor COC through the internal PMOS pull-up. The slope is determined by COC. 7. When the FAULT_EN pin is brought low, if the fault condition still exists, the latched FAULT pin will be pulled low by the internal 3mA current source. When fault condition is removed then the Fault pin charges as shown in step 6. 8. At this point there is a fault condition, and the part is enabled before the FAULT pin can charge to VCC. This shortens the user-set delay, so the fault is latched earlier. The new delay time can be calculated by equation 1, after substituting the voltage seen on the FAULT pin for VCC. 2 2 2 Vcc 2V 0V Fault_En Input OC Fault Condition (Active High) 1 4 8 6 1 4 5 6 1 4 7 6 4 3 |
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