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L6470H 数据表(PDF) 31 Page - STMicroelectronics |
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L6470H 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 70 page ![]() L6470 Functional description Doc ID16737 Rev 5 31/70 6.14 Programmable DMOS slew rate, deadtime and blanking time Using the POW_SR parameter in the CONFIG register, it is possible to set the commutation speed of the power bridges output (see Table 26, Section 9.1.21). 6.15 Integrated analog-to-digital converter The L6470 integrates an NADC bit ramp-compare analog-to-digital converter with a reference voltage equal to VREG. The analog-to-digital converter input is available through the ADCIN pin and the conversion result is available in the ADC_OUT register (see Section 9.1.16). Sampling frequency is equal to the programmed PWM frequency. The ADC_OUT value can be used for motor supply voltage compensation or can be at the user’s disposal. 6.16 Internal voltage regulator The L6470 integrates a voltage regulator which generates a 3 V voltage starting from the motor power supply (VSA and VSB). In order to make the voltage regulator stable, at least 22 µF should be connected between the VREG pin and ground (suggested value is 47 µF). The internal voltage regulator can be used to supply the VDD pin in order to make the device digital output range 3.3 V compatible (Figure 14). A digital output range, 5 V compatible, may be obtained connecting the VDD pin to an external 5 V voltage source. In both cases, a 10 µF capacitance should be connected to the VDD pin in order to obtain a correct operation. The internal voltage regulator is able to supply a current up to IREG,MAX, internal logic consumption included (Ilogic). When the device is in Standby mode, the maximum current that can be supplied is IREG, STBY, internal consumption included (Ilogic, STBY). If an external 3.3 V regulated voltage is available, it can be applied to the VREG pin in order to supply all the internal logic and to avoid power dissipation of the internal 3 V voltage regulator (Figure 14). The external voltage regulator should never sink current from the VREG pin. Figure 13. External switch connection |
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