PCF8574_PCF8574A

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Product data sheet

Rev. 5 — 27 May 2013

9 of 33

NXP Semiconductors

PCF8574; PCF8574A

8.3 Reading from a port (Input mode)

The port must have been previously written to logic 1, which is the condition after

power-on reset. To enter the Read mode the master (microcontroller) addresses the slave

device and sets the last bit of the address byte to logic 1 (address byte read). The slave

will acknowledge and then send the data byte to the master. The master will NACK and

then send the STOP condition or ACK and read the input register again.

The read of any pin being used as an output will indicate HIGH or LOW depending on the

actual state of the pin.

If the data on the input port changes faster than the master can read, this data may be

lost. The DATA 2 and DATA3 are lost because these data did not meet the setup time and

hold time (see Figure 9).

Simple code for Read mode:

<S> <slave address + read> <ACK> <data in> <ACK> ... <data in> <ACK> <data in>

<NACK> <P>

Remark: Bold type = generated by slave device.

8.4 Power-on reset

power-on reset cycle.

A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at

any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input

data is lost.

Fig 9.

Read mode (input)

A5 A4 A3 A2 A1 A0

1

A

SA6

slave address

START condition

R/W

acknowledge

from slave

002aah383

data from port

A

acknowledge

from master

SDA

1

no acknowledge

from master

read from

port

data at

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

P

STOP

condition

DATA 1