DocID023111 Rev 2

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H3LIS331DL

Mechanical and electrical specifications

38

2.3

Communication interface characteristics

2.3.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

3. When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.

Table 5. SPI slave timing values

Symbol

Parameter

Unit

Min.

Max.

SPI clock cycle

100

ns

SPI clock frequency

10

MHz

CS setup time

6

ns

CS hold time

8

SDI input setup time

5

SDI input hold time

15

SDO valid output time

50

SDO output hold time

9

SDO output disable time

50

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production.