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DAC08CSZ 数据表(PDF) 9 Page - Analog Devices

部件名 DAC08CSZ
功能描述  8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface)
PDF  12 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

DAC08CSZ 数据表(HTML) 9 Page - Analog Devices

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REV. B
DAC08
–9–
14
15
LOW T.C.
4.5k
39k
VREF
10V
APPROX
5k
IREF(+) 2mA
10k
POT
1V
Figure 11. Recommended Full-Scale Adjustment Circuit
14
15
RREF
4
2
IO
IO
NOTE
RREF SETS IFS; R15 IS FOR
BIAS CURRENT CANCELLATION.
R15
–VREF
–VREF
RREF
IFS
Figure 12. Basic Negative Reference Operation
14
IREF(+) = 2.000mA
4
2
MSB
B1 B2 B3 B4 B5 B6 B7
LSB
B8
IO
IO
EO
EO
10.000k
10.000k
10.000V
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
ZERO-SCALE –LSB
NEG. FULL-SCALE +LSB
NEG. FULL-SCALE
B1
1
1
1
1
0
0
0
B2
1
1
0
0
1
0
0
B3
1
1
0
0
1
0
0
B4
1
1
0
0
1
0
0
B5
1
1
0
0
1
0
0
B6
1
1
0
0
1
0
0
B7
1
1
0
0
1
0
0
B8
1
0
1
0
1
1
0
EO
–9.920
–9.840
–0.080
0.000
+0.080
+9.920
+10.000
EO
+10.000
+9.920
+0.160
+0.080
0.000
–9.840
–9.920
Figure 10. Basic Bipolar Output Operation
MSB
B1 B2 B3 B4 B5 B6
LSB
B8
4
2
B7
IO
IO
EO
5.000k
5.0k
10V
REF01*
*OR ADR01
4
2
6
5
V+
V–
CC
VLC
10k
+15V –15V
–15V
OP711
+15V
5.0k
15V
VO
POS. FULL RANGE
ZERO-SCALE
NEG. FULL-SCALE +1 LSB
NEG. FULL-SCALE
B1
1
1
0
0
B2
1
0
0
0
B3
1
0
0
0
B4
1
0
0
0
B5
1
0
0
0
B6
1
0
0
0
B7
1
0
0
0
B8
1
0
1
0
EO
+4.960
0.000
–4.960
–5.000
Figure 13. Offset Binary Operation
4
2
IO
IO
EO
0 TO +IFR
RL
RL
OP711
IFR =
IREF
255
256
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO
GROUND.
Figure 14. Positive Low Impedance Output Operation
4
2
IO
IO
EO
0 TO –IFR
RL
OP711
IFR =
IREF
255
256
RL
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4)
TO GROUND.
Figure 15. Negative Low Impedance Output Operation
VLC
1
TTL, DTL
VTH = 1.4V
15V
9.1k
6.2k
0.1 F
VTH = V LC 1.4V
15V CMOS
VTH = 7.6V
VLC
13k
39k
ECL
“A”
2N3904
3k
2N3904
TO PIN 1
VLC
6.2k
–5.2V
20k
20k
V+
“A”
2N3904
3k
2N3904
TO PIN 1
VLC
R3
400 A
CMOS, HTL, NMOS
TEMPERATURE COMPENSATING V LC CIRCUITS
Figure 16. Interfacing with Various Logic Families



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