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MMPF0100NPEP 数据表(PDF) 19 Page - Freescale Semiconductor, Inc |
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MMPF0100NPEP 数据表(HTML) 19 Page - Freescale Semiconductor, Inc |
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19 / 137 page  Analog Integrated Circuit Device Data Freescale Semiconductor 19 PF0100 Functional Block Requirements and Behaviors Start-up VGEN4_SEQ 3 7 3 3 VGEN5_VOLT 2.5 V 2.8 V 2.5 V 2.5 V VGEN5_SEQ 3 12 5 5 VGEN6_VOLT 2.8 V 3.3 V - - VGEN6_SEQ 3 8 - - PU CONFIG, SEQ_CLK_SPEED 1.0 ms 2.0 ms 1.0 ms 1.0 ms PU CONFIG, SWDVS_CLK 6.25 mV/ s 1.5625 mV/ s 12.5 mV/ s12.5 mV/s PU CONFIG, PWRON Level sensitive SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz SW1C CONFIG 2.0 MHz SW2 CONFIG 2.0 MHz SW3A CONFIG SW3AB Single Phase, 2.0 MHz SW3B CONFIG 2.0 MHz SW4 CONFIG No VTT, 2.0 MHz PG EN RESETBMCU in Default Mode Table 8. Start-up Configuration Registers Default Configuration Pre-programmed OTP Configuration All Devices F0 F1 F2 |
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