AD7685

Rev. C | Page 18 of 28

CS MODE 3-WIRE, NO BUSY INDICATOR

This mode is usually used when a single AD7685 is connected

to an SPI-compatible digital host.

The connection diagram is shown in Figure 34, and the

corresponding timing is given in Figure 35.

With SDI tied to VIO, a rising edge on CNV initiates a

conversion, selects the CS mode, and forces SDO to high

impedance. Once a conversion is initiated, it will continue to

completion irrespective of the state of CNV. For instance, it

could be useful to bring CNV low to select other SPI devices,

such as analog multiplexers, but CNV must be returned high

before the minimum conversion time and held high until the

maximum conversion time to avoid the generation of the BUSY

signal indicator. When conversion is completed, the AD7685

enters the acquisition phase and powers down. When CNV

goes low, the MSB is output onto SDO. The remaining data bits

are then clocked by subsequent SCK falling edges. The data is

valid on both SCK edges. Although the rising edge can be used

to capture the data, a digital host using the SCK falling edge will

allow a faster reading rate provided it has an acceptable hold

time. After the 16th SCK falling edge or when CNV goes high,

whichever is earlier, SDO returns to high impedance.

CNV

SCK

SDO

SDI

DATA IN

CLK

CONVERT

VIO

DIGITAL HOST

AD7685

Figure 34. CS Mode 3-Wire, No BUSY Indicator

Connection Diagram (SDI High)

SDO

D15

D14

D13

D1

D0

SCK

1

2

3

14

15

16

CNV

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)