ADP122/ADP123

Data Sheet

Rev. E | Page 12 of 24

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP122/ADP123 are designed for operation with small,

space-saving ceramic capacitors, but these devices can function

with most commonly used capacitors as long as care is taken to

ensure an appropriate effective series resistance (ESR) value. The

ESR of the output capacitor affects the stability of the LDO control

loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or

less is recommended to ensure stability of the ADP122/ADP123.

The transient response to changes in load current is also affected by

the output capacitance. Using a larger value of output capacitance

improves the transient response of the ADP122/ADP123 to

dynamic changes in load current. Figure 32 and Figure 33 show

the transient responses for output capacitance values of 1 µF and

4.7 µF, respectively.

W

CH2 50.0mV

B

W

M 400ns A CH1

196mA

1

2

T

14.80%

1mA TO 300mA LOAD STEP

CH1

W

CH2 20.0mV

M 400ns

A CH1

196mA

1

2

T

15.00%

1mA TO 300mA LOAD STEP

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the circuit

sensitivity to the printed circuit board (PCB) layout, especially

when a long input trace or high source impedance is encountered.

If greater than 1 µF of output capacitance is required, the input

capacitor should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the ADP122/

ADP123, as long as the capacitor meets the minimum capacitance

and maximum ESR requirements. Ceramic capacitors are manu-

factured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors must have an

adequate dielectric to ensure the minimum capacitance over the

necessary temperature range and dc bias conditions. Using an

X5R or X7R dielectric with a voltage rating of 6.3 V or 10 V is

recommended. However, using Y5V and Z5U dielectrics is not

recommended for any LDO, due to their poor temperature and

dc bias characteristics.

Figure 34 depicts the capacitance vs. capacitor voltage bias charac-

teristics of a 0603, 1 µF, 6.3 V X5R capacitor. The voltage stability of

a capacitor is strongly influenced by the capacitor size and the

voltage rating. In general, a capacitor in a larger package or of a

higher voltage rating exhibits better stability. The temperature

variation of the X5R dielectric is about ±15% over the −40°C to

+85°C temperature range and is not a function of package or

voltage rating.

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

0

1

2

3

4

5

6

7

BIAS VOLTAGE (V)

Figure 34. Capacitance vs. Capacitor Voltage Bias Characteristics

Equation 1 can be used to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

(1)

where:

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

C is 0.96 μF at 4.2 V from the graph in Figure 34.

Substituting these values in Equation 1 yields