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AD5544BCPZ-R2 数据表(PDF) 17 Page - Analog Devices

部件名 AD5544BCPZ-R2
功能描述  Quad, Current-Output, Serial-Input 16-/14-Bit DACs
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5544BCPZ-R2 数据表(HTML) 17 Page - Analog Devices

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Data Sheet
AD5544/AD5554
Rev. G | Page 17 of 24
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
INPUT
REGISTER R
DAC A
B
C
D
2:4
DECODE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
EN
16
DAC D
REGISTER R
DAC C
REGISTER R
DAC B
REGISTER R
DAC A
REGISTER R
POWER-
ON
RESET
DAC B
DAC C
DAC D
DAC A
AD5544
VREFA B C D
VDD
RFBA
IOUTA
AGNDA
RFBB
IOUTB
AGNDB
RFBC
IOUTC
AGNDC
RFBD
IOUTD
AGNDD
AGNDF
DGND
MSB
VSS
SET
MSB
SET
MSB
SDO
SDI
CLK
CS
RS
LDAC
Figure 23. System Level Digital Interfacing
EN
SHIFT REGISTER
ADDRESS
DECODER
A
B
C
D
TO INPUT REGISTER
19TH/17TH
CLOCK
SDO
SDI
CLK
CS
Figure 24. AD5544/AD5554 Equivalent Logic Interface
POWER-ON RESET
When the VDD power supply is turned on, an internal reset strobe
forces all the input and DAC registers to the zero-code state or
half-scale state, depending on the MSB pin voltage. The VDD power
supply should have a smooth positive ramp without drooping to
have consistent results, especially in the region of VDD = 1.5 V to
2.3 V. The VSS supply has no effect on the power-on reset perform-
ance. The DAC register data stays at a zero-scale or half-scale
setting until a valid serial register data load takes place.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zener
diodes that are connected to ground (DGND) and VDD, as
shown in Figure 25.
VDD
DIGITAL
INPUTS
5k
DGND
Figure 25. Equivalent ESD Production Circuits
POWER SUPPLY SEQUENCE
As standard practice, it is recommended that VDD, VSS, and ground
be powered up prior to any reference. The ideal power-up sequence
is as follows: AGNDx, DGND, VDD, VSS, VREFx, and the digital inputs.
A noncompliance power-up sequence may elevate the reference
current, but the devices resume normal operation once VDD and
VSS are powered up.



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