ADXL375 datasheet(13/32 Pages) AD

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Data Sheet

ADXL375

Rev. 0 | Page 13 of 32

INTERRUPTS

The ADXL375 provides two output pins for driving interrupts:

INT1 and INT2. Both interrupt pins are push-pull, low impedance

pins (see Table 10 for output specifications). The default config-

uration of the interrupt pins is active high. The polarity can be

changed to active low by setting the INT_INVERT bit (Bit D5)

in the DATA_FORMAT register (Address 0x31). All interrupt

functions can be enabled simultaneously, but some functions

may need to share the same interrupt pin.

ENABLING AND DISABLING INTERRUPTS

Interrupts are enabled by setting the appropriate bits in the

INT_ENABLE register (Address 0x2E); the interrupt is mapped

to the INT1 pin or the INT2 pin based on the contents of the

INT_MAP register (Address 0x2F). When the user configures

the interrupt pins for the first time, it is recommended that the

functions and interrupt mapping be configured before the

interrupts are enabled.

When changing the configuration of an interrupt, follow this

procedure.

1. Disable the interrupt by clearing the bit corresponding

to the function in the INT_ENABLE register.

2. Reconfigure the interrupt function.

3. Reenable the interrupt in the INT_ENABLE register.

Configuration of the functions while the interrupts are disabled

helps to prevent the accidental generation of an interrupt.

CLEARING INTERRUPTS

The interrupt functions are latched and can be cleared as follows:

1. Read the data registers (Address 0x32 to Address 0x37)

to clear the data-related interrupts.

2. Read the INT_SOURCE register (Address 0x30) to clear

the remaining interrupts.

BITS IN THE INTERRUPT REGISTERS

This section describes the interrupts that can be set in the

INT_ENABLE register (Address 0x2E) and monitored in the

INT_SOURCE register (Address 0x30).

For an in-depth description of the FIFO buffer and the inter-

rupt bits, see the AN-1025 Application Note, Utilization of the

First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital

Accelerometers.

DATA_READY Bit

The DATA_READY bit is set when new data is available and

is cleared when no new data is available.

SINGLE_SHOCK Bit

The SINGLE_SHOCK bit is set when a single acceleration event

that is greater than the value in the THRESH_SHOCK register

(Address 0x1D) occurs for less time than is specified by the DUR

Detection section.

DOUBLE_SHOCK Bit

The DOUBLE_SHOCK bit is set when two acceleration events

that are greater than the value in the THRESH_SHOCK register

(Address 0x1D) occur for less time than is specified by the DUR

time specified by the latent register (Address 0x22) but within

the time specified by the window register (Address 0x23). For

more information, see the Shock Detection section.

Activity Bit

The activity bit is set when acceleration greater than the value

stored in the THRESH_ACT register (Address 0x24) is experi-

enced on any participating axis. Participating axes are specified

by the ACT_INACT_CTL register (Address 0x27).

Table 10. Interrupt Pin Digital Output Specifications

Limit1

Parameter

Test Conditions/Comments

Min

Max

Unit

DIGITAL OUTPUT

Low Level Output Voltage (VOL)

IOL = 300 µA

0.2 × VDD I/O

High Level Output Voltage (VOH)

IOH = −150 µA

0.8 × VDD I/O

Low Level Output Current (IOL)

VOL = VOL, MAX

300

µA

High Level Output Current (IOH)

VOH = VOH, MIN

−150

µA

PIN CAPACITANCE

fIN = 1 MHz, VS = 2.5 V

RISE/FALL TIME

CLOAD = 150 pF

Rise Time (tR)2

210

Fall Time (tF)3

150

Limits based on characterization results; not production tested.

Rise time is measured as the transition time from VOL,MAX to VOH, MIN of the interrupt pin.

Fall time is measured as the transition time from VOH,MIN to VOL,MAX of the interrupt pin.

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