9

Atmel AT24C128C [DATASHEET]

8734B–SEEPR–9/2012

7.

Device Addressing

The 128K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or

write operation (Figure 7-1). The device address word consists of a mandatory one, zero sequence for the first four most

significant bits as shown. This is common to all 2-wire EEPROM devices.

Figure 7-1. Device Addressing

The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same bus. These

that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return

to a standby state.

Data Security: AT24C128C has a hardware data protection scheme that allows the user to write protect the whole

1

0

1

0

A2A1A0

R/W

MSB

LSB