AD5227

Rev. B | Page 11 of 1

6

reached the maximum or minimum scale. If one ignores the

effect of the wiper resistance, the transfer functions can be

simplified as

A

WB

V

CP

V

64

+

=

Δ

U/D = 1

(3)

A

WB

V

CP

V

64

−

=

Δ

U/D = 0

(4)

Unlike rheostat mode operation where the absolute tolerance is

high, potentiometer mode operation yields an almost ratiometric

function of CP/64 with a relatively small error contributed by

ratiometric adjustment also reduces the overall temperature

dominates.

Potentiometer mode operation includes an op amp gain

configuration among others. The A, W, and B terminals can be

input or output terminals and have no polarity constraint

DIGITAL INTERFACE

The AD5227 contains a 3-wire serial input interface. The three

inputs are clock (CLK), chip select (CS), and up/down control

(U/D). These inputs can be controlled digitally for optimum

speed and flexibility

When CS is pulled low, a clock pulse increments or decrements

the up/down counter. The direction is determined by the state

of the U/D pin. When a specific state of the U/D remains, the

device continues to change in the same direction under con-

secutive clocks until it comes to the end of the resistance

setting. All digital inputs, CS, CLK, and U/D pins, are protected

with a series input resistor and a parallel Zener ESD structure as

shown in

.

Figure 28

1k

Ω

LOGIC

Figure 28. Equivalent ESD Protection Digital Pins

TERMINAL VOLTAGE OPERATION RANGE

The AD5227 is designed with internal ESD protection diodes

(Figure 29), but the diodes also set the boundary of the terminal

operating voltages. Voltage present on Terminal A, B, or W that

GND.

POWER-UP AND POWER-DOWN SEQUENCES

Because of the ESD protection diodes, it is important to power

powered unintentionally and can affect the rest of the system

and digital inputs.

GND

A

W

B

LAYOUT AND POWER SUPPLY BIASING

It is a good practice to use compact, minimum lead length

layout design. The leads to the input should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance. It is also good

practice to bypass the power supplies with quality capacitors.

Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum

or electrolytic capacitors should be applied at the supplies to

minimize any transient disturbance and filter low frequency

ripple.

Figure 30 illustrates the basic supply bypassing configuration

for the AD5227. The ground pin of the AD5227 is a digital

ground reference that should be joined to the common ground

at a single point to minimize the digital ground bounce.

+

GND

AD5227

C2

10

μF

C1

0.1

μF

Figure 30. Power Supply Bypassing