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S12CPUV2D 数据表(PDF) 2 Page - Freescale Semiconductor, Inc |
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S12CPUV2D 数据表(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 126 page  Revision History Version Number Revision Date Effective Date Author Description of Changes V01.00 16 NOV 2001 19 NOV 2001 Initial version based on MC9SDP256-2.09 Version. V01.01 18 FEB 2002 18 FEB 2002 In table 7 I/O Characteristics" of the electrical characteristics replaced tPULSE with tpign and tpval in lines "Port ... Interrupt Input Pulse filtered" and "Port ... Interrupt Input Pulse passed" respectively. V01.02 6 MAR 2002 6 MAR 2002 Table "Oscillator Characteristics": removed "Oscillator start-up time from POR or STOP" row Table "5V I/O Characteristics": Updated Partial Drive IOH = +–2mA and Full Drive IOH = –10mA Table "ATD Operating Characteristics": Distinguish IREFfor 1 and 2 ATD blocks on Table "ATD Electrical Characteristics": Update CINS to 22 pF Table "Operating Conditions": Changed VDD and VDDPLL to 2.35 V (min) Removed Document number except from Cover Sheet Updated Table "Document References" V01.03 4 June 2002 4 June 2002 Table "5V I/O Characteristics" : Corrected Input Capacitance to 6pF Section: "Device Pinout" (112-pin and 80-pin): added in diagrams RXCAN0 to PJ6 and TXCAN0 to PJ7 Table "PLL Characteristics": Updated parameters K1 and f1 Figure "Basic PLL functional diagram": Inserted XFC pin in diagram Enhanced section "XFC Component Selection" Added to Sections ATD, ECT and PWM: freeze mode = active BDM mode V01.04 4 July 2002 4 July 2002 Added 1L86D to Table "Assigned Part ID numbers" Corrected MEMSIZ1 value in Table "Memory size registers" Subsection "Device Memory Map: Removed Flash mapping from $0000 to $3FFF. Table "Signal Properties": Added column "Internal Pull Resistor". Preface Table "Document References": Changed to full naming for each block. Table "Interrupt Vector Locations", Column "Local Enable": Corrected several register and bit names. V01.05 30 July 2002 30 July 2002 Figure "Recommended PCB Layout for 80QFP: Corrected VREGEN pin position Thermal values for junction to board and package BGND pin pull-up Part Order Information Global Register Table Chip Configuration Summary Modified mode of Operations chapter Section "Printed Circuit Board Layout Proposals": added Pierce Oscillator examples for 112LQFP and 80QFP |
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