AD7863ARS-3 datasheet(5/24 Pages) AD

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AD7863

Rev. B | Page 5 of 24

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter1, 2

A, B Versions

Unit

Test Conditions/Comments

tCONV

5.2

μs max

Conversion time

tACQ

0.5

μs max

Acquisition time

Parallel Interface

ns min

CS to RD setup time

ns min

CS to RD hold time

ns min

CONVST pulse width

ns min

RD pulse width

t53

ns min

Data access time after falling edge of RD

t64

ns min

Bus relinquish time after rising edge of RD

ns max

ns min

Time between consecutive reads

400

ns min

Quiet time

1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2 See Figure 2.

3 Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

VA1

VA2

VB1

VB2

CONVST

BUSY

DATA

tCONV = 5.2µs

tACQ

Figure 2. Timing Diagram

TO OUTPUT

1.6mA

200µA

50pF

Figure 3. Load Circuit for Access Time and Bus Relinquish Time

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