Revision History

Revision

Date

Revision

Description

Aug 2002

0.25

• Initial Release.

Sep 2002

0.75

• Changed package diagram to molded plastic BGA.

• Added DC/AC specifications.

• Corrected pinout information.

Oct 2002

1.0

• Identified FIFO as 64 KB and verified ballout tables.

July 2003

1.5

• Added 82547GI coverage.

• Signals CLKR_CAP and XTAL_CAP changed to RSVD_NC and NC, respectively.

Oct 2004

2.0

• Added Architecture Overview chapter.

• Update signal names to match Design Guide and EEPROM Map and Program-

ming Application Note.

Nov 2004

2.1

• Updated lead-free information.

• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate

to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and

Pinout Information.

• Added statement that no changes to existing soldering processes are needed for

the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack-

age Information”.

Jan 2005

2.2

• Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See

Table 2, Recommended Operating Conditions and Table 6, DC Characteristics.

Apr 2005

2.3

• Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is

not used then an external pull-down resistor is required.

June 2006

2.4

• Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is

not used then an external pull-up resistor is required.

Aug 2006

2.5

• Removed note “b” from Table 2 and note “a” from Tables 3 and 4.

• Moved the note following Table 5 before Table 3.

Aug 2007

2.6

• Replace Intel logo, updated the Product Features title page, and document order-

ing information.

Dec 2007

2.7

• Updated Section 3.3. Removed the internal pullup device text from the FLASH

Serial Data Output / LAN Disable pin description.

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