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PIC16F1459-ESLSQTP 数据表(PDF) 21 Page - Microchip Technology |
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PIC16F1459-ESLSQTP 数据表(HTML) 21 Page - Microchip Technology |
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21 / 418 page  2012 Microchip Technology Inc. Preliminary DS41639A-page 21 PIC16(L)F1454/5/9 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • Automatic Interrupt Context Saving • 16-level Stack with Overflow and Underflow • File Select Registers • Instruction Set FIGURE 2-1: CORE BLOCK DIAGRAM Data Bus 8 14 Program Bus Instruction reg Program Counter 8 Level Stack (13-bit) Direct Addr 7 12 Addr MUX FSR reg STATUS reg MUX ALU Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT 8 8 12 3 Internal Oscillator Block Configuration Data Bus 8 14 Program Bus Instruction reg Program Counter 8 Level Stack (13-bit) Direct Addr 7 Addr MUX FSR reg STATUS reg MUX ALU W Reg Instruction Decode & Control Timing Generation 8 8 3 Internal Oscillator Block Configuration 15 Data Bus 8 14 Program Bus Instruction Reg Program Counter 16-Level Stack (15-bit) Direct Addr 7 RAM Addr Addr MUX Indirect Addr FSR0 Reg STATUS Reg MUX ALU Instruction Decode and Control Timing Generation 8 8 3 Internal Oscillator Block Configuration Flash Program Memory RAM FSR reg FSR reg FSR1 Reg 15 15 15 Program Memory Read (PMR) 12 FSR reg FSR reg BSR Reg 5 Power-up Timer Power-on Reset Watchdog Timer VDD Brown-out Reset VSS VDD VSS VDD VSS |
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