PFS7323L datasheet(3/30 Pages) POWERINT

3 / 30 page

Rev. B 06/13

PFS7323-7329

www.powerint.com

Pin Functional Description

VOLTAGE MONITOR (V) Pin:

The VOLTAGE MONITOR pin is tied to the rectified high-voltage

DC rail through a large resistor (4 M

W ±1%) to minimize power

dissipation and standby power consumption. Modifying this

resistor value affects peak power limit, brown-in/out thresholds

and will degrade input current quality (reduce power factor and

increase THD). A small ceramic capacitor (22 nF) is required

from the VOLTAGE MONITOR pin to SIGNAL GROUND pin to

bypass any switching noise present on the rectified DC bus.

This pin also features brown-in/out detection thresholds.

REFERENCE (R) Pin:

This pin is connected to an external precision resistor and is used for

an internal current reference source in the controller. The external

resistor is tied between the REFERENCE and SIGNAL GROUND

pins. The REFERENCE pin only has two valid resistor values to

select ‘Full’ (24.9 k

W ±1%) and ‘Efficiency’ (49.9 kW ±1%) power

modes. A precision resistor with the values specified above must

be selected since this sets the internal current reference for the

controller. Other values beyond what is specified may adversely

effect the operation of the device. A bypass capacitor is also

recommended across the REFERENCE pin resistor to the SIGNAL

GROUND pin. For ‘Full’ power mode (24.9 k

W) a capacitor

value of 470 pf and 1 nF for the ‘Efficiency’ mode with 49.9 k

SIGNAL GROUND (G) Pin:

Discrete components used in the feedback circuit, including

loop compensation, decoupling capacitors for the supply (VCC)

and line-sense (V) must be referenced to the SIGNAL GROUND

pin. The SIGNAL GROUND pin is also connected to the tab of

the device.

The SIGNAL GROUND pin must not be tied to

the SOURCE pin.

COMPENSATION (C) Pin:

This pin is used for loop compensation and voltage feedback.

The COMPENSATION pin is a high input-impedance reference

terminal that connects to the main voltage regulation feedback

resistor divider network. This pin also connects to the loop

compensation components comprising of a series RC network.

A 22 nF capacitor is also required between the COMPENSATION

and SIGNAL GROUND pins; this capacitor must be placed very

close to the device on the PCB to bypass any switching noise.

FEEDBACK (FB) Pin:

This pin is connected to the main voltage regulation feedback

resistor divider network and is used for fast over and under-

voltage protection. This pin also detects the presence of the

main voltage divider network at start-up.

POWER GOOD THRESHOLD (PGT) Pin:

This pin is used to program the output voltage threshold where

the PG signal becomes ‘high-impedance’ representing the PFC

stage falling out of regulation. The low threshold for the PG

signal is programmed with a resistor between the POWER

GOOD THRESHOLD and SIGNAL GROUND pins.

POWER GOOD (PG) Pin:

This pin is an open-drain connection that indicates that the

output voltage is in regulation. At start-up, once the FEEDBACK

pin voltage has risen to ~95% of the set output voltage, the

POWER GOOD pin is pulled low. After start-up the output

voltage threshold at which the PG signal becomes high-

impedance depends on the threshold programmed by the

POWER GOOD THRESHOLD pin resistor.

BIAS POWER (VCC) Pin:

This is a 10.2-13 VDC bias supply used to power the IC. The

bias voltage must be externally clamped to prevent the BIAS

POWER pin from exceeding 15 VDC.

SOURCE (S) Pin:

This pin is the source connection of the power switch.

DRAIN (D) Pin:

This is the drain connection of the internal power switch.

BOOST DIODE CATHODE (K) Pin: (eSIP-16 package only)

This is the cathode connection of the internal Qspeed Diode.

PI-6789-022213

H Package (eSIP-16D)

(Front View)

H Package

(eSIP-16D)

(Back View)

L Package (eSIP-16G)

(Front View)

Exposed Pad (Backside)

Internally Connected to

GROUND (G) Pin

Exposed Metal (Both H and L

Packages) (On Package Edge)

Internally Connected to G Pin

Pin 1 I.D.

Exposed Pad

(Backside)

Not Shown

Figure 2.

Pin Configuration.

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