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Error Amplifier Block (see fig. 17b):

The Error Amplifier (E/A) inverting input is used in primary feedback technique to compare a partition of the volt-

age generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regu-

lation (see "Application Ideas", fig. 24). With secondary feedback (typically using a TL431 at the secondary side

and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the

E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Ap-

plication Ideas", fig. 23).

The E/A output is used typically for control loop compensation, realized with an RC network connected to the

inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded

optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 23 in "Ap-

plication Ideas").

Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 17b):

The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the

programming signal delivered by the feedforward block, determines the exact time when the external MOSFET

is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the

noise generated ("double-pulse suppression").

A comparator senses the voltage on the current sense input and disables the gate driver if the voltage at the pin

exceeds 2 V. Such anomalous condition is typically generated by a short circuit on the secondary rectifier or on

the secondary winding. To re-enable the driver, first the IC must be turned off and then can be restarted, that is

the Vcc voltage must fall below the UVLO threshold.

When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming

from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time.

Then the device will initiate a new start-up cycle. In case of failure of the secondary diode the resulting behavior

will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.

Gate Driver (see fig. 18):

A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a

high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to

prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative.

An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the ex-

ternal MOSFET cannot be turned on accidentally (e.g. at power-on).

Figure 18. Gate driver with UVLO pull-down

7

6

8

GD

UVLO

GND

DRIVER

Vcc

Q

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