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CDCU877ARTB 数据表(PDF) 3 Page - Texas Instruments

部件名 CDCU877ARTB
功能描述  1.8-V PHASE LOCK LOOP CLOCK DRIVER
PDF  23 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCU877ARTB 数据表(HTML) 3 Page - Texas Instruments

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CDCU877,, CDCU877A
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS688D – JUNE 2005 – REVISED JULY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
GQL/ZQL
RHA/RTB
AGND
G1
7
Analog ground
AVDD
H1
8
Analog power
CK
E1
4
I
Clock input with a (10 k
Ω to 100 kΩ) pulldown resistor
Complementary clock input with a (10 k
Ω to 100 kΩ) pulldown
CK
F1
5
I
resistor
FBIN
E6
27
I
Feedback clock input
FBIN
F6
26
I
Complementary feedback clock input
FBOUT
H6
24
O
Feedback clock output
FBOUT
G6
25
O
Complementary feedback clock output
OE
F5
22
I
Output enable (asynchronous)
OS
D5
21
I
Output select (tied to GND or VDD)
B2, B3, B4, B5,
GND
C2, C5, H2, H5,
10
Ground
J2, J3, J4, J5
D2, D3, D4, E2,
1, 6, 9, 15, 20, 23,
VDDQ
E5, F2, G2, G3,
Logic and output power
28, 31, 36
G4, G5
A2, A1, D1, J1, K3,
3, 11, 14, 16, 19,
Y[0:9]
O
Clock outputs
A5, A6, D6, J6, K4
29, 33, 34, 38, 39
A3, B1, C1, K1,
2, 12, 13, 18, 17,
Y[0:9]
K2, A4, B6, C6,
O
Complementary clock outputs
30, 32, 35, 37, 40
K6, K5
FUNCTION TABLE
INPUTS
OUTPUTS
AVDD
OE
OS
CK
CK
Y
Y
FBOUT
FBOUT
PLL
GND
H
X
L
H
L
H
L
H
Bypassed/Off
GND
H
X
H
L
H
L
H
L
Bypassed/Off
GND
L
H
L
H
LZ
LZ
L
H
Bypassed/Off
LZ
LZ
GND
L
L
H
L
H
L
Bypassed/Off
Y7 Active
Y7 Active
1.8 V Nominal
L
H
L
H
LZ
LZ
L
H
On
LZ
LZ
1.8 V Nominal
L
L
H
L
H
L
On
Y7 Active
Y7 Active
1.8 V Nominal
H
X
L
H
L
H
L
H
On
1.8 V Nominal
H
X
H
L
H
L
H
L
On
1.8 V Nominal
X
X
L
L
LZ
LZ
LZ
LZ
Off
X
X
X
H
H
Reserved
3
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