MCR03EZPFX4021 datasheet(15/36 Pages) IRF

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IR3837MPbF

Rev 1.31

Soft-Start

The IR3837 has a digital internal soft-start to

control the output voltage rise and to limit the

current surge at the start-up. To ensure correct

start-up, the soft-start sequence initiates when

the Enable and Vcc rise above their UVLO

thresholds and generate the Power On Ready

(POR) signal. The internal SS signal linearly

rises with the rate of 0.2mV / µs from 0V to 2V.

Figure 6 shows the waveforms during soft start

(also refer to figure 11). The normal start up time

is fixed, and is equal to:

During the soft start the OCP is enabled to

protect the device for any short circuit and over

current condition.

Fig. 6. Theoretical operation waveforms

during soft-start (non tracking / non sequencing)



(1)

3ms

0.2mV/

0.7V

1.3V

start





Operating Frequency

The switching frequency can be programmed

between 250kHz – 1500kHz by connecting an

external resistor from R

t pin to Gnd. Table 1

tabulates the oscillator frequency versus R

Shutdown

The IR3837 can be shutdown by pulling the

Enable pin below its 0.85 V threshold. This will

tri-state both, the high side driver as well as the

low side driver.

Table 1. Switching Frequency and I

OCSet vs.

External Resistor (R

Over-Current Protection

The over current protection is performed by

sensing current through the R

DS(on) of the sync

FET. This method enhances the converter’s

efficiency and reduces cost by eliminating a

current sense resistor. As shown in figure 7, an

external resistor (R

OCSet) is connected between

OCSet pin and the switch node (SW) which sets

the current limit set point.

An internal current source sources current

(IOCSet ) out of the OCSet pin. This current is a

function of Rt and hence, of the free-running

switching frequency.

Table 1. shows IOCSet at different switching

frequencies.

The

internal

current

source

develops a voltage across R

OCSet. When the sync

FET is turned on, the inductor current flows

through Q2 and results in a voltage at OCSet

which is given by:

An over current is detected if the OCSet pin goes

below ground. However, to avoid false tripping ,

due to the noise generated when the sync FET is

turned on, the OCP comparator is enabled about

200ns after sync-FET is turned on.

)

(on

OCSet

.(3)

..........

)

(

)

(









.....(2)

..........

)

(





OCSet

700

71.7

1400

9.76

75.15

1500

9.31

55.1

1100

12.7

60.85

1200

11.5

65.4

1300

10.7

48.95

1000

14.3

44.3

900

15.8

39.3

800

17.8

34.1

700

20.5

29.54

600

23.7

24.35

500

28.7

19.6

400

35.7

300

47.5

Iocset (μA)

Fs (kHz)

Rt (kΩ)