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PCF8564AU/5GC/1 数据表(PDF) 20 Page - NXP Semiconductors

部件名 PCF8564AU/5GC/1
功能描述  Real time clock and calendar
PDF  48 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8564AU/5GC/1 数据表(HTML) 20 Page - NXP Semiconductors

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PCF8564A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 26 August 2013
20 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
[1]
Registers marked ‘x’ are undefined at power-on and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a circuit has been implemented to
disable the POR and speed up functional test of the module. The setting of this mode
requires that the I2C signals on the pins SDA and SCL are toggled as illustrated in
Figure 10. All timings shown are required minimums.
Once the override mode has been entered, the chip immediately stops, being reset, and
normal operation may begin, i.e., entry into the EXT_CLK test mode via I2C access. The
override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1
before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal
operation has no effect, except to prevent entry into the POR override mode.
Table 28.
Register reset values[1]
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_1
00001000
01h
Control_2
00000000
02h
Seconds
1
xxxxxxx
03h
Minutes
xxxxxxxx
04h
Hours
xxxxxxxx
05h
Days
xxxxxxxx
06h
Weekdays
xxxxxxxx
07h
Months
xxxxxxxx
08h
Years
xxxxxxxx
09h
Minute_alarm
1
xxxxxxx
0Ah
Hour_alarm
1
xxxxxxx
0Bh
Day_alarm
1
xxxxxxx
0Ch
Weekday_alarm
1
xxxxxxx
0Dh
CLKOUT_ctrl
1
xxxxx0
0
0Eh
Timer_ctrl
0
xxxxx1
1
0Fh
Timer
xxxxxxxx
Allow 500 ns between the edges of either signal.
Fig 10. POR override sequence



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