LTC1290BCSW datasheet(13/32 Pages) LINER

13 / 32 page

LTC1290

1290fe

APPLICATI

I FOR ATIO

MSB-First/LSB-First Format (MSBF)

The output data of the LTC1290 is programmed for MSB-

first or LSB-first sequence using the MSBF bit. For MSB

first output data the input word clocked to the LTC1290

should always contain a logical one in the sixth bit location

(MSBF bit). Likewise for LSB-first output data the input

word clocked to the LTC1290 should always contain a zero

in the MSBF bit location. The MSBF bit affects only the

order of the output data word. The order of the input word

is unaffected by this bit.

MSBF

OUTPUT FORMAT

LSB First

MSB First

Word Length (WL1, WL0) and Power Shutdown

The last two bits of the input word (WL1 and WL0)

program the output data word length and the power

shutdown feature of the LTC1290. Word lengths of 8, 12

or 16 bits can be selected according to the following table.

The WL1 and WL0 bits in a given DIN word control the

length of the present, not the next, DOUT word. WL1 and

WL0 are never “don’t cares” and must be set for the

correct DOUT word length even when a “dummy” DIN word

is sent. On any transfer cycle, the word length should be

made equal to the number of SCLK cycles sent by the

MPU. Power down will occur when WL1 = 0 and WL0 = 1

is selected. The previous conversion result will be clocked

out as a 10 bit word so a “dummy” conversion is required

before powering down the LTC1290. Conversions are

resumed once CS goes low or an SCLK is applied, if CS is

already low.

WL1

WL0

OUTPUT WORD LENGTH

8-Bits

Power Shutdown

12-Bits

16-Bits

Deglitcher

A deglitching circuit has been added to the Chip Select

input of the LTC1290 to minimize the effects of errors

caused by noise on that input. This circuit ignores changes

in state on the CS input that are shorter in duration than

one ACLK cycle. After a change of state on the CS input, the

LTC1290 waits for two falling edge of the ACLK before

recognizing a valid chip select. One indication of CS

recognition is the DOUT line becoming active (leaving the

Hi-Z state). Note that the deglitching applies to both the

rising and falling CS edges.

CS Low During Conversion

In the normal mode of operation, CS is brought high

during the conversion time. The serial port ignores any

SCLK activity while CS is high. The LTC1290 will also

operate with CS low during the conversion. In this mode,

SCLK must remain low during the conversion as shown in

the following figure. After the conversion is complete, the

DOUT line will become active with the first output bit. Then

the data transfer can begin as normal.

Low CS Recognized Internally

High CS Recognized Internally

DOUT

LTC1290 • AI07

ACLK

VALID OUTPUT

HI-Z

DOUT

LTC1290 • AI06

ACLK

VALID OUTPUT

HI-Z

LTC1290BCSW 数据表(PDF) 13 Page - Linear Technology

LTC1290BCSW 数据表(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载