Hi-Speed USB Transceiver with 1.8V ULPI Interface - 19.2MHz Reference Clock

7

Revision 2.1 (06-10-10)

PRODUCT PREVIEW

15

C5

DATA[2]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

16

B4

DATA[1]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

17

B5

DATA[0]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[0] is

the LSB.

18

A5

NXT

Output,

CMOS

High

The PHY asserts NXT to throttle the data.

When the Link is sending data to the

PHY, NXT indicates when the current

byte has been accepted by the PHY. The

Link places the next byte on the data bus

in the following clock cycle.

19

A4

DIR

Output,

CMOS

N/A

Controls the direction of the data bus.

When the PHY has data to transfer to the

Link, it drives DIR high to take ownership

of the bus. When the PHY has no data to

transfer it drives DIR low and monitors

the bus for commands from the Link.

20

A3

STP

Input,

CMOS

High

The Link asserts STP for one clock cycle

to stop the data stream currently on the

bus. If the Link is sending data to the

PHY, STP indicates the last byte of data

was on the bus in the previous cycle.

21

B3

VDD1.8

Power

N/A

External 1.8V Supply input pin. This pad

needs to be bypassed with a 0.1uF

capacitor to ground, placed as close as

possible to the USB3316.

22

B2

RESETB

Input,

CMOS,

Low

When low, the part is suspended with all

of the I/O tri-stated. When high the

USB3316 will operate as a normal ULPI

device.

23

A2

REFCLK

Input,

CMOS

N/A

19.2MHz Reference Clock input.

24

A1

RBIAS

Analog,

CMOS

N/A

Bias Resistor pin. This pin requires an

8.06kΩ (±1%) resistor to ground, placed

as close as possible to the USB3316.

FLAG

C3

GND

Ground

N/A

Ground.

QFN only: The flag should be connected

to the ground plane with a via array

under the exposed flag. This is the main

ground for the IC.

Table 1 USB3316 Pin Description (continued)

PIN/

BALL

NAME

DIRECTION/

TYPE

ACTIVE

LEVEL

DESCRIPTION